----------------------------------------------------------------------------------
-- INSTITUTION:    Xidian University
-- DESIGNER:       Yuan Xiaoguang & Ren Aifeng    
-- 
-- Create Date:    16:53:58 02-14-2016 
-- Design Name:    PWM_COUNTER 
-- Module Name:    PWM_COUNTER
-- Project Name:   PWM
-- Target Devices: EP3C16F484C6
-- Tool versions:  Quartus II 13.1
-- Design Lauguage:VHDL
-- Dependencies:   -
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: DE0 Board Input Freguency = 50 MHz
--                      Destiny Output  Freguency =  1 Hz
--
----------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity PWM_COUNTER is
	generic(
		cnt_mod_value: INTEGER := 100     --计数器模值为100，110位计数器
	);
	port(--输入输出端口
		i_pwm_clk: in STD_LOGIC;
		i_sys_rst: in STD_LOGIC;	   --系统复位输入
		o_pwm_val: out STD_LOGIC_VECTOR (6 downto 0) --灯输出信号，6 downto 0说明是7位
	);
end entity PWM_COUNTER;

architecture behavior of PWM_COUNTER is
	signal r_pwm_val: STD_LOGIC_VECTOR (6 downto 0);    --定义控制LED灯的信号
begin
	process(i_sys_rst,i_pwm_clk)	 --敏感变量，也就是
		begin        
		if (i_sys_rst = '1') then	   --当输入系统复位高有效时
				r_pwm_val <= "0000000";      --熄灭所有LED灯。赋值
			elsif (i_pwm_clk'event AND i_pwm_clk = '1') then	 --当检测到clk上升沿输出为1
			if (r_pwm_val = cnt_mod_value-1) then   --当信号计数计到011，也就是3的时候
					r_pwm_val <= "0000000";       --熄灭所有LED灯
				else
					r_pwm_val <= r_pwm_val+1;      --信号还没计数到011，就加1
				end if;
			end if;
	end process;
	o_pwm_val <= r_pwm_val;     --赋值给输出
end architecture behavior;
